
Fresh insights on low latency and high frequency trading. Mostly new relevant technology, C++, FPGA, Verilog, tutorials, short notes and of course, rants. Problem subscribing? Try https://lucisqr.lemonsqueezy.com/buy/c78e2dd6-81c0-44cd-bfa3-13db7158a050
| Platform | Pricing | Freemium | Publishes | Daily | |
|---|---|---|---|---|---|
| Issues | 305 | Founded | 4 years ago | Last Issue | 5 days ago |
| Active | |||||

Internally a hive is a linked list of blocks with geometrically growing capacities. Each block carries a skipfield, a small per-slot counter that tells the iterator how many erased slots to jump in one add, so iteration never walks dead ele...
Map the same block of memory twice, right next to itself, and a ring buffer’s wrap-around just… vanishes. Every read and write becomes one clean, contiguous span — no branch, no split, no copy. It’s the most seductive trick in low-latency s...
A paper that went up on arXiv two days ago reports that inserting 500,000 keys into a deliberately overloaded C hash table takes 271.5 seconds with linked-list buckets and 121.2 seconds with “hybrid-batch” buckets. A 2.2x gap. I read the so...
AMD formally launches Zen 6 on Tuesday, July 22, leading with the server part, and by Wednesday the coverage will have mixed the keynote numbers, the leaks, and two-year-old news into one undifferentiated pile.
Before that happens, it is a...
There is a small proposal sitting in the SG1 pile for Brno, P4221R0, authored by Maged Michael, Paul McKenney, and Michael Wong. Three people who have spent more of their lives than most thinking about what a memory operation is allowed to...
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The writers behind this newsletter.
I earned MSc, PhD in Structural Dynamics, with emphasis in supercomputing. Switched to high frequency trading at Citadel in early 2000s. I work mostly with trading applications. LightQR Suite: www.vitorian.com
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