
Fresh insights on low latency and high frequency trading. Mostly new relevant technology, C++, FPGA, Verilog, tutorials, short notes and of course, rants. Problem subscribing? Try https://lucisqr.lemonsqueezy.com/buy/c78e2dd6-81c0-44cd-bfa3-13db7158a050
| Platform | Pricing | Only free issues | Publishes | Daily | |
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| Issues | 355 | Founded | 4 years ago | Last Issue | 2 days ago |
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Two loops, same task: lowercase a buffer in place and report the first non-ASCII byte. One has a break statement. One does not. On an isolated Zen 2 core with g++-14 -O3, the one doing strictly more work is 26x faster.
GitHub engineering...
We’ve built three FPGA challenges, graded the same way as the C++ ones: hidden tests in simulation within minutes, and a nightly Vivado timing run on an Alveo U50.
FPGA 01 is a cut-through UDP echo (Verilog or C++ with Vitis HLS), FPGA 02...
Twelve of twenty. That is how many voting national bodies approved the C++26 draft international standard, against the fourteen it needed, and nine of the twenty-two bodies that voted said no, against a ceiling of five. Robert Seacord, conv...
Link: https://www.amazon.com/Low-Latency-Trading-Insights-Measured/dp/B0HM1PQP2V
“Pass small structs by value.” “A computed goto beats a switch.” “Turn the prefetchers off.” Thirteen rules every low-latency engineer repeats, measured on ei...
GCC 16 made C++20 the default. It also changed the C++20 ABI that GCC 13, 14 and 15 shipped as “experimental”. Measured across a real upgrade boundary: every std::atomic wait and every counting_semaphore that crosses GCC 15/16 in one proces...
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The writers behind this newsletter.
I earned MSc, PhD in Structural Dynamics, with emphasis in supercomputing. Switched to high frequency trading at Citadel in early 2000s. I work mostly with trading applications. LightQR Suite: www.vitorian.com
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