What are you optimizing for?
FPRoxComputer Architecture, Computer Arithmetic, RISC-V
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fprox.substack.comLatest Issues
RISC-V's Zvzip is Changing
This quick post (it could have been a note) surveys and illustrates recent changes to a fast track specification under development: Zvzip. The post assumes basic knowledge about RISC-V Vector (if you need a refresher you may want to conside...
Manifest for RISC-V Constant Time Floating-Point Operations
Disclaimer: this post summarizes a proposal that spawned out of multiple discussions in RISC-V PQC Task Group and FP SIG. The post itself represents my own suggestions and has not been endorsed by any of those groups; all mistakes are my ow...
RISC-V and Floating-Point
RISC-V support for floating-point arithmetic is a topic we have partially covered in a few previous posts but we felt like it deserves a full overview post of its own.
RISC-V base ISA (RV32I or RV64I) does not define any floating-point ins...
Emulating future RISC-V Vector extensions
Lately, I have been considering the following problem: how to develop an application example for a future RISC-V (Vector) extension with no fast hardware support yet ?
Usually, I would rely on an instruction set simulator (like spike) and...
RISC-V Vector Is Expanding
Updated July 10th, 2026: Zvzip spec draft has changed substantially. We added an explicit mention of the version (v0.1) described in this post.
A little under a year ago (assuming we do not take too long to write this piece) we published a...
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