What are you optimizing for ? (fprox's substack)
FproxComputer Architecture, Computer Arithmetic, RISC-V
| Platform |  | Pricing | Only free issues | Publishes | Monthly |
|---|---|---|---|---|---|
| Issues | 50 | Subscribers | Read | fprox.substack.com |
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Latest Issues
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Accelerating CRC with RISC-V Vector
In this post we describe a way to compute a cycle redundancy check (CRC) hash using RISC-V Vector extension (a.k.a. RVV). This application is well suited for being optimized with one of the recently ratified vector cryptographic extension, ...
Unpacking the CanMV K230 RISC-V board
RISC-V ISA is almost 15-year old and RISC-V hardware has been popping up regularly for a while. Until recently it was difficult to find a board with RISC-V Vector support, in particular ratified RVV 1.0 support (there have been a few earlie...
RISC-V Scalar Bit Manipulation Extensions
On March 25th 2024 (announcement) the public review period for RISC-V B extension ended and it should be ratified soon. We want to use this occasion to present RISC-V ISA offerings in term of scalar bit manipulation.
Partial Taxonomy of 8-bit Floating-Point Formats
This blog post is not centered on RISC-V, it reviews recent developments in Floating-Point arithmetic around the standardization of small (8-bit) floating-point formats.
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Authors
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Computer architecture and computer arithmetic enthusiast
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