
EE Master's degree holder. 30+ years of extensive experience in telecom and high-speed data (BB CPE, 5G Wireless). Focused on high-speed communication solutions for data centers and telecom, with interest in advanced process and packaging now.
| Platform | Pricing | Only free issues | Publishes | Weekly | |
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| Issues | 69 | Founded | a year ago | Last Issue | 8 days ago |
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隨著生成式 AI 叢集與大型加速器對運算頻寬的渴求呈指數級增長,Scale-up 與 Scale-out 網路架構正承受前所未有的吞吐壓力。回顧高速 SerDes 演進史,通道傳輸速率翻倍的開發週期已從過去的 5 至 6 年急劇壓縮至 3 年以內。當產業剛完成 224G 世代的技術鋪設,邁向單通道 448 Gbps 的標準制定與工程落地便已迫在眉睫。
在高速互連領域扮演先鋒偵察角色的 OIF(Optical Internetworking Forum),近年來持續推進 CE...
隨著 AI 模型參數規模與運算叢集持續爆發,傳統以單機櫃為核心的運算範式正邁向跨機架(Multi-Rack)乃至跨排(Multi-Row)的 Scale-Up 架構。在單通道 SerDes 速率邁向 224G 與 448G 的節點上,銅線傳輸面臨嚴峻的通道損耗斷崖(Channel Loss Cliff)、粗重線徑與散熱阻礙,驅使高速互連全面由銅走向光學架構。
為應對這場傳輸典範轉移,產業在 OFC 2026 期間同天宣告成立了涵蓋 XPO、Open CPX 與 OCI 的三...
隨著生成式 AI 模型的參數規模呈幾何級數擴展,運算加速晶片對算力密度、高頻寬記憶體(HBM)容量以及晶粒間互連頻寬的需求急劇攀升。為了突破先進製程在物理微縮與光罩尺寸上的限制,半導體架構全面朝向 2.5D/3D 小晶片(Chiplet)異質整合與晶圓級系統(System-on-Wafer, SoW)演進。中介層封裝面積正由現行 3.3 倍光罩向 8 倍乃至 14 倍光罩以上持續延伸。
然而,在大尺寸高密度封裝的發展路徑上,傳統有機載板正面臨難以克服的物理瓶頸:
Than...
在生成式 AI 推論架構的演進中,提示處理(Prefill)與逐字生成(Decode)兩個階段展現了截然不同的物理運算特性:Prefill 階段屬於高度算力密集的矩陣乘法(Compute-Bound GEMM),高度依賴稠密算力與大容量 HBM 處理長上下文;而自迴歸逐字輸出的 Decode 階段則屬於極度頻寬受限的矩陣-向量運算(Memory Bandwidth-Bound GEMV),傳統 GPU 往往因受困於記憶體牆(Memory Wall)而導致算力大幅閒置。
面對...
在大型語言模型(LLM)的擴展定律(Scaling Law)與屋頂線模型(Roofline Model)相互推動下,生成式 AI 的運算瓶頸已轉向資料傳輸端。特別是在自回歸生成的 Decode 階段,模型權重與龐大 KV Cache 的頻繁搬移,使運算強度大幅降低,系統深陷記憶體受限(Memory-Bound)的物理邊界。面對光罩極限(Reticule Limit)與片上 SRAM 微縮趨緩帶來的成本壁壘,具備 2.5D/3D 先進封裝與極高頻寬密度的高頻寬記憶體(High...
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The writers behind this newsletter.
EE Master's degree holder. 30+ years of extensive experience in telecom and high-speed data (BB CPE, 5G Wireless). Focused on high-speed communication solutions for data centers and telecom, with interest in advanced process and packaging.
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