Enabling AI Infrastructure co-design from chip to cluster through insights from industry-leading experts across the stack. Simplified, never dumbed down.
| Platform |  | Pricing | Freemium | Publishes | Weekly |
|---|---|---|---|---|---|
| Issues | 39 | Founded | 10 months ago | Last Issue | 8 days ago |
| Active | |||||
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siliconcodesign.comLatest Issues
OCP 2026 - Co-Designing an AI Cluster
AI Compute Racks need three things to process tokens and survive: Power, cooling, and data. To maximize compute density, all three systems needs to be scaled alongside compute power and the plumbing need to be co-designed to work safety and...
Why Hybrid Bonding Is Very Difficult to Manufacture at Scale
Why submicron interconnects require extreme precision in CMP, alignment, and surface preparation, and how defects determine yield
Hybrid bonding promises to dramatically increase interconnect density, signal bandwidth, and enable more comp...
Why Optical Testing Could Become the Biggest Bottleneck in CPO Manufacturing
How wafer-level probing, optical alignment, known-good engines, and automated test equipment constrain high-volume production.
Unlike electrical testing for semiconductors, automating optical test is extremely difficult because of the gene...
Why More GPU and HBM Bandwidth Doesn't Solve AI's Data Movement Bottleneck
How disaggregated inference shifts the bottleneck across scale-up, scale-out, memory tiers, and system orchestration.
Bottlenecks never disappear; they just shift to another layer of the stack.
Co-Packaged Optics for 224Gbps+ Scale-Up: An All-In-One Overview
A system breakdown of challenges for every technology component of CPO: packaging, PIC, laser, and EIC
Quick Housekeeping Note: I’ll be a media partner for IMAPS and SiPh Symposium in Boston, MA from Sept 28 - Oct 2. The theme is “Intellig...
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Authors
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Deep-Tech Semiconductor Analyst, MSEE. Educating engineers on the complete AI datacenter hardware stack from pure fundamentals.
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