Expert-driven interdisciplinary deep-dives into the AI HW Infrastructure stack from first principles
| Platform |  | Pricing | Freemium | Publishes | Weekly |
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| Issues | 32 | Founded | 8 months ago | Last Issue | 11 days ago |
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A System-Level Overview of Scale-up AI Infrastructure Racks (Part 1: Network Architecture)
This post is written to give system-context for the high-speed interconnect of AI rack architectures in preparation for Hot Interconnects and Hot Chips 2026.
In part 1, I provide an overview of the network architecture:
- Front-End and...
A Deep Dive into SRAM: The Staging Ground of LLM Inference
Fundamentals of SRAM and how SRAM constraints affect array size scaling and LLM inference performance
In this post I will cover the following topics on SRAM:
Design Automation Conference 2026 - The Bottlenecks that Limit AI Use in Chip Design
AI is EDA is not as effective as pundits claim it to be, for now. Artour Levin, CVP AI Silicon Engineering, Microsoft, “EDA Opportunities in building high performance AI accelerators” DAC 2026
Note: 8/21/26: I am making this post complete...
A Comprehensive Overview of the AI Accelerator Landscape: From Digital to Analog Compute-in-Memory Architectures
A survey of major AI accelerator categories, and a deep dive into the scaling challenges with Analog Compute-in-memory
Editors Note: (7/22/26): I trimmed the paywall to only paywall the scaling challenges with Analog CiM. This way, you can...
A Comprehensive Deep Dive into High-Speed HBM5 Interconnect: Signal Integrity and Co-Design Challenges
How transmission line effects and power-supply induced jitter make high-speed HBM interconnect scaling one of the most challenging co-design issues in AI racks
While a lot of attention is being drawn to the current HBM4 shortage, this post...
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Authors
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Deep-Tech Semiconductor Analyst, MSEE. Educating engineers on the complete AI datacenter hardware stack from first principles.
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