Expert-driven interdisciplinary deep-dives into the AI HW Infrastructure stack from pure fundamentals
| Platform |  | Pricing | Freemium | Publishes | Weekly |
|---|---|---|---|---|---|
| Issues | 35 | Founded | 9 months ago | Last Issue | 9 days ago |
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siliconcodesign.comLatest Issues
Co-Packaged Optics for 224Gbps+ Scale-Up: An All-In-One Overview
A system breakdown of challenges for every technology component of CPO: packaging, PIC, laser, and EIC
Quick Housekeeping Note: I’ll be a media partner for IMAPS and SiPh Symposium in Boston, MA from Sept 28 - Oct 2. The theme is “Intellig...
The System Architecture of HBM: How Thermals, Signal Integrity, and Reliability Limit Scaling
An advanced co-design deep dive from fundamentals to 3D integration
In this advanced deep dive, I will discuss the challenges of scaling HBM performance.
An Advanced System Architecture Breakdown of OpenAI’s Jalapeno Inference Accelerator
Begin with the end goal in mind: how user experience defined the architecture and how agentic coding methods contributed to the shortened chip design timeline
At the end of the Hot Chips 2026 conference, OpenAI presented their chip archite...
A System-Level Overview of Scale-up AI Infrastructure Racks (Part 1: Network Architecture)
This post is written to give system-context for the high-speed interconnect of AI rack architectures in preparation for Hot Interconnects and Hot Chips 2026.
In part 1, I provide an overview of the network architecture:
- Front-End and...
A Deep Dive into SRAM: The Staging Ground of LLM Inference
Fundamentals of SRAM and how SRAM constraints affect array size scaling and LLM inference performance
In this post I will cover the following topics on SRAM:
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Authors
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Deep-Tech Semiconductor Analyst, MSEE. Educating engineers on the complete AI datacenter hardware stack from pure fundamentals.
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