
AI infrastructure research across photonics, memory, interconnects, power, and packaging. Engineering depth translated for professionals and investors.
| Platform | Pricing | Freemium | Publishes | Twice weekly | |
|---|---|---|---|---|---|
| Issues | 180 | Founded | 3 years ago | Last Issue | 6 days ago |
| Active | |||||

How an InP DFB laser works, and the four physical walls that make high power hard.
There is a lot of FUD in the market about ultra high power (UHP) lasers for CPO and who the leading provider is in this segment. Everybody I’ve asked about...
An engineering-first read of the supposed Kyber delay, why NVL72x2 was the "odd" duck nobody wanted, how to actually deploy it, and why CPO is the ultimate answer for large world sizes.
In a July 6 X post, SemiAnalysis reported that Nvidia...
HBC stacking DRAM on the compute die increases memory bandwidth and skips CoWoS. The packaging problem does not go away, it shifts to 3D.
At its 2026 Investor Day, Qualcomm introduced High Bandwidth Compute (HBC), which is DRAM stacked on...
This week was a big one for OpenAI with ChatGPT 5.6 Sol being released, and their inference accelerator Jalapeno being announced. Qualcomm also held its much awaited investor day ever since they refused to reveal much at Computex. Mainstrea...
KV cache storage is a distinct workload that requires SSDs designed for it. Number of cell levels, block sizes, and data placements all matter, and some SSD flash makers are actually getting it right.
Earlier, we have covered NAND as a sto...
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